Low leakage decoder using dual-threshold technique for static random-access memory applications

Decoders are one of the significant peripheral components static random-access memory (SRAM). As CMOS technology moves towards nano scale regime, leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm technology. Leakage is reduced by employing dual-threshold technique. Dual thresholding a technique that uses transistors two different threshold voltages. The implemented simulation methods; first method with voltage and second substrate biasing to vary voltage. Row column designed simulated H-Spice. calculated compared for both methods. gate Method-1 Method-2 provides maximum savings 87.67% 90.81% respectively. 96.76% 98.74% reported row decoder Similarly, gives 97.09% 99.11% decoder. difference Method-at same 3.14%, 1.98%, 2.02% gate,